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this is information on a product in full production. april 2015 docid024483 rev 4 1/20 STGIPS20C60-H sllimm? small low-loss intelligent molded module ipm, 3-phase inverter - 20 a, 600 v short-circuit rugged igbt datasheet - production data features ? ipm 20 a, 600 v 3-phase igbt inverter bridge including control ics for gate driving and free- wheeling diodes ? short-circuit rugged igbts ? 3.3 v, 5 v, 15 v cmos/ttl inputs comparators with hysteresis and pull-down / pull-up resistors ? undervoltage lockout ? internal bootstrap diode ? interlocking function ? smart shutdown function ? comparator for fault protection against overtemperature and overcurrent ? dbc leading to low thermal resistance ? isolation rating of 2500 v rms /min ? ul recognized: ul1557 file e81734 applications ? 3-phase inverters for motor drives ? air conditioners description this intelligent power module provides a compact, high performance ac motor drive in a simple, rugged design. combining st proprietary control ics with the most advanced short-circuit- rugged igbt system technology, this device is ideal for 3-phase inverters in applications such as motor drives and air conditioners. sllimm? is a trademark of stmicroelectronics. sdip-25l table 1. device summary order code marking package packing STGIPS20C60-H gips20c60-h sdip-25l tube www.st.com
contents STGIPS20C60-H 2/20 docid024483 rev 4 contents 1 internal block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . 3 2 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4 smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 sdip-25l package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
docid024483 rev 4 3/20 STGIPS20C60-H internal block diagram and pin configuration 20 1 internal block diagram and pin configuration figure 1. internal block diagram am05002v3 w nw p vboot u vboot w out v vboot v out u out w lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ pin 16 pin 1 p p pin 17 pin 25 gnd lin-u hin-v lin-v hin-w hin-u lin-w cin vcc nu nv u v lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ sd/od
internal block diagram and pin configuration STGIPS20C60-H 4/20 docid024483 rev 4 figure 2. pin layout (bottom view) table 2. pin description pin n symbol description 1out u high-side reference output for u phase 2v bootu bootstrap voltage for u phase 3lin u low-side logic input for u phase 4hin u high-side logic input for u phase 5v cc low voltage power supply 6out v high-side reference output for v phase 7v boot v bootstrap voltage for v phase 8 gnd ground 9lin v low-side logic input for v phase 10 hin v high-side logic input for v phase 11 out w high-side reference output for w phase 12 v boot w bootstrap voltage for w phase 13 lin w low-side logic input for w phase 14 hin w high-side logic input for w phase 15 sd / od shutdown logic input (active low) / open-drain (comparator output) 16 cin comparator input 17 n w negative dc input for w phase 18 w w phase output 19 p positive dc input 20 n v negative dc input for v phase 21 v v phase output 22 p positive dc input 23 n u negative dc input for u phase 24 u u phase output 25 p positive dc input 0$5.,1*$5($
docid024483 rev 4 5/20 STGIPS20C60-H electrical ratings 20 2 electrical ratings 2.1 absolute maximum ratings table 3. inverter part symbol parameter value unit v pn supply voltage applied between p - n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p - n u , n v , n w 500 v v ces each igbt collector emitter voltage (v in (1) = 0) 1. applied between hin i , lin i and gnd for i = u, v, w 600 v i c each igbt continuous collector current at t c = 25c 20 a i cp (2) 2. pulse width limited by max junction temperature each igbt pulsed collector current 40 a p tot each igbt total dissipation at t c = 25c 46 w t scw short circuit withstand time, v ce = 0.5 v (br)ces t j = 125 c, v cc = v boot = 15 v, v in (1) = 0 - 5 v 5s table 4. control part symbol parameter value unit v out output voltage applied between out u, out v, out w - gnd v boot - 21 to v boot + 0.3 v v cc low voltage power supply - 0.3 to +21 v v cin comparator input voltage - 0.3 to v cc +0.3 v v boot bootstrap voltage applied between v boot i - out i for i = u, v, w - 0.3 to 620 v v in logic input voltage applied between hin, lin and gnd - 0.3 to 15 v v sd /od open drain voltage - 0.3 to 15 v dv out /dt allowed output slew rate 50 v/ns table 5. total system symbol parameter value unit v iso isolation withstand voltage applied between each pin and heatsink plate (ac voltage, t = 60 sec.) 2500 v t j power chips operating junction temperature - 40 to 150 c t c module case operation temperature - 40 to 125 c
electrical ratings STGIPS20C60-H 6/20 docid024483 rev 4 2.2 thermal data table 6. thermal data symbol parameter value unit r thjc thermal resistance junction-case single igbt 2.7 c/w thermal resistance junction-case single diode 5 c/w figure 3. maximum i c(rms) current vs. switching frequency (1) figure 4. maximum i c(rms) current vs. f sine (1) 1. simulated curves refer to typical igbt parameters and maximum r thj-c. am17108v1 12 14 16 18 20 22 24 26 28 i c(rms) (a) 4 8 12 16 f sw (khz) 3 -phase sinusoidal pwm v pn = 300 v, modulaon index = 0.8, pf = 0.6, t j = 150 c, f sine = 60 hz tc = 80 c tc = 100 c am17109v1 8 9 10 11 12 13 14 15 16 17 i c(rms) (a) 1 10 100 f sine (hz) 3 - phase sinusoidal pwm v pn = 300 v, modulation index = 0.8, pf = 0.6, t j = 150 c, t c = 100 c fsw = 12 khz fsw = 16 khz fsw = 20 khz
docid024483 rev 4 7/20 STGIPS20C60-H electrical characteristics 20 3 electrical characteristics t j = 25 c unless otherwise specified. note: t on and t off include the propagation delay time of the internal drive. t c(on) and t c(off) are the switching time of igbt itself under the internally given gate driving condition. table 7. inverter part symbol parameter test conditions value unit min. typ. max. v ce(sat) collector-emitter saturation voltage v cc = v boot = 15 v, v in (1) = 0 5 v, i c = 20 a -1.6 2 v v cc = v boot = 15 v, v in (1) = 0 5 v, i c = 20 a, t j = 125 c -1.7 i ces collector-cut off current (v in (1) = 0 ?logic state?) v ce = 550 v, v cc = v boot = 15 v - 100 a v f diode forward voltage v in (1) = 0 ?logic state?, i c = 20 a - 1.9 2.2 v inductive load switching time and energy t on turn-on time v pn = 300 v, v cc = v boot = 15 v, v in (1) = 0 5 v, i c = 20 a (see figure 5 ) -390 - ns t c(on) crossover time (on) - 170 - t off turn-off time - 970 - t c(off) crossover time (off) - 150 - t rr reverse recovery time - 284 - e on turn-on switching losses - 520 - j e off turn-off switching losses - 460 - 1. applied between hin i , lin i and gnd for i = u, v, w.
electrical characteristics STGIPS20C60-H 8/20 docid024483 rev 4 figure 5. switching time test circuit figure 6. switching time definition figure 4 ?switching time definition" refers to hin, lin inputs (active high). am17138v1 vboot>vcc rsd l ic vce +5v vcc input 0 1 bus lin /sd hin vcc dt lvg hvg out boot cp+ gnd v ce i c i c v in t on t c(on) v in(on) 10% i c 90% i c 10% v ce (a) turn-on (b) turn-off t rr 100% i c 100% i c v in v ce t off t c(off) v in(off) 10% v ce 10% i c am09223v1
docid024483 rev 4 9/20 STGIPS20C60-H electrical characteristics 20 3.1 control part table 8. low voltage power supply (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v cc_hys v cc uv hysteresis 1.2 1.5 1.8 v v cc_thon v cc uv turn on threshold 11.5 12 12.5 v v cc_thoff v cc uv turn off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 10 v sd /od = 5 v; lin = hin = 0, c in = 0 450 a i qcc quiescent current v cc = 15 v sd /od = 5 v; lin = hin = 0, c in = 0 3.5 ma v ref internal comparator (cin) reference voltage 0.5 0.54 0.58 v table 9. bootstrapped voltage (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v bs_hys v bs uv hysteresis 1.2 1.5 1.8 v v bs_thon v bs uv turn on threshold 11.1 11.5 12.1 v v bs_thoff v bs uv turn off threshold 9.8 10 10.6 v i qbsu undervoltage v bs quiescent current v bs < 9 v sd /od = 5 v; lin = 0 hin = 5 v; c in = 0 70 110 a i qbs v bs quiescent current v bs = 15 v sd /od = 5 v; lin = 0 hin = 5 v; c in = 0 200 300 a r ds(on) bootstrap driver on resistance lin= 5 v; hin= 0 v 120 ? table 10. logic inputs (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v il low level logic threshold voltage 0.8 1.1 v v ih high level logic threshold voltage 1.9 2.25 v i hinh hin logic ?1? input bias current hin = 15 v 20 40 100 a i hini hin logic ?0? input bias current hin = 0 v 1 a i linh lin logic ?1? input bias current lin = 15 v 20 40 100 a i lini lin logic ?0? input bias current lin = 0v 1 a i sdh sd logic ?0? input bias current sd = 15 v 30 120 300 a i sdl sd logic ?1? input bias current sd = 0 v 3 a dt dead time see figure 7 and table 13 1.2 s
electrical characteristics STGIPS20C60-H 10/20 docid024483 rev 4 note: x: don?t care table 11. sense comparator characteristics (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit i ib input bias current v cin = 1 v - 3 a v ol open-drain low-level output voltage i od = 3 ma - 0.5 v t d_comp comparator delay sd /od pulled to 5 v through 100 k resistor - 90 130 ns sr slew rate c l = 180 pf; r pu = 5 k -60 v/sec t sd shut down to high / low side driver propagation delay v out = 0, v boot = v cc , v in = 0 to 3.3 v 50 125 200 ns t isd comparator triggering to high / low side driver turn-off propagation delay measured applying a voltage step from 0 v to 3.3 v to pin cin 50 200 250 table 12. truth table condition logic input (v i ) output sd /od lin hin lvg hvg shutdown enable half-bridge tri-state lxxll interlocking half-bridge tri-state hhhl l 0 ??logic state? half-bridge tri-state hllll 1 ?logic state? low side direct driving hhlhl 1 ?logic state? high side direct driving hlhlh
docid024483 rev 4 11/20 STGIPS20C60-H electrical characteristics 20 3.2 waveform definitions figure 7. dead time and interlocking waveforms definition interl ocking interl ocking interl ocking interl ocking g
smart shutdown function STGIPS20C60-H 12/20 docid024483 rev 4 4 smart shutdown function the STGIPS20C60-H integrates a comparator for fault sensing purposes. the comparator has an internal voltage reference v ref connected to the inverting input, while the non- inverting input, available on pin (c in ), can be connected to an external shunt resistor in order to implement a simple over-current protection function. when the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the halfbridge in tri-state. in the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a rc network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. the time delay between the fault and the outputs turn-off is no more dependent on the rc values of the external network connected to the shutdown pin. at the same time the dmos connected to the open-drain output (pin sd /od) is turned on by the internal logic which holds it on until the shutdown voltage is lower than the logic input lower threshold (v il ). finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external rc network.
docid024483 rev 4 13/20 STGIPS20C60-H smart shutdown function 20 figure 8. smart shutdown timing waveforms please refer to table 11 for internal propagation delay time details. sd/od from/to controller v bias c sd r sd smart sd logic r on_od shut down circuit r pd_sd an approximation of the disable time is given by: where: hin/lin hvg/lvg open drain gate (internal) comp vref cp+ protection fast shut down : the driver outputs are set in sd state immediately after the comparator triggering even if the sd signal has not yet reach the lower input threshold disable time sd/od am12947v1
application information STGIPS20C60-H 14/20 docid024483 rev 4 5 application information figure 9. typical application circuit am05001v3 cvcc w nw lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ vboot v p out u vboot u out v vboot w out w rg lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ lin sd/od vcc gnd dt out hvg vboot hin lvg cp+ rg rdt rg cdt rg rg rg controller cvcc rdt cdt cvcc r c rsd vdc m csd + 3.3v/5v line cbu cbv cbw vcc rshunt gnd hin-u lin-u sd/od hin-w lin-v hin-v lin-w cin vcc nu nv t1 t2 t3 t4 t5 rdt t6 v u cdt d1 d2 d3 d4 d5 d6
docid024483 rev 4 15/20 STGIPS20C60-H application information 20 5.1 recommendations ? input signals hin, lin are active high logic. a 375 k (typ.) pull down resistor is built-in for each input. if an external rc filter is used, for noise immunity, pay attention to the variation of the input signal level. ? to prevent the input signals oscillation, the wiring of each input should be as short as possible. ? by integrating an application specific type hvic inside the module, direct coupling to mcu terminals without any opto-coupler is possible. ? each capacitor should be located as nearby the pins of ipm as possible. ? low inductance shunt resistors should be used for phase leg current sensing. ? electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. ? the sd /od signal should be pulled up to 5 v / 3.3 v with an external resistor (see section 4: smart shutdown function for detailed info). note: for further details refer to an3338. table 13. recommended operating conditions symbol parameter conditions value unit min. typ. max. v pn supply voltage applied between p-nu,nv,nw 300 400 v v cc control supply voltage applied between v cc -gnd 13.5 15 18 v v bs high side bias voltage applied between v booti -out i for i=u,v,w 13 18 v t dead blanking time to prevent arm-short for each input signal 1.5 s f pwm pwm input signal -40c < t c < 100c -40c < t j < 125c 20 khz t c case operation temperature 100 c
package information STGIPS20C60-H 16/20 docid024483 rev 4 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. please refer to dedicated technical note tn0107 for mounting instructions. 6.1 sdip-25l package information figure 10. sdip-25l package outline b
docid024483 rev 4 17/20 STGIPS20C60-H package information 20 table 14. sdip-25l mechanical data dim. mm min. typ. max. a 43.90 44.40 44.90 a1 1.15 1.35 1.55 a2 1.40 1.60 1.80 a3 38.90 39.40 39.90 b 21.50 22.00 22.50 b1 11.25 11.85 12.45 b2 24.83 25.23 25.63 c 5.00 5.40 6.00 c1 6.50 7.00 7.50 c2 11.20 11.70 12.20 c3 2.90 3.00 3.10 e 2.15 2.35 2.55 e1 3.40 3.60 3.80 e2 4.50 4.70 4.90 e3 6.30 6.50 6.70 d 33.30 d1 5.55 e11.20 e1 1.40 f 0.85 1.00 1.15 f1 0.35 0.50 0.65 r 1.55 1.75 1.95 t 0.45 0.55 0.65 v0 6
package information STGIPS20C60-H 18/20 docid024483 rev 4 6.2 packing information figure 11. sdip-25l packing information am10488v1 base quantity: 11 pcs bulk quantity: 132 pcs 8123127_e
docid024483 rev 4 19/20 STGIPS20C60-H revision history 20 7 revision history table 15. document revision history date revision changes 09-apr-2013 1 initial release 08-jul-2013 2 updated v f typ value in table 7: inverter part and dt value in table 10: logic inputs (vcc = 15 v unless otherwise specified) . 14-may-2014 3 document status promoted from preliminary to production data. updated table 3: inverter part , table 6: thermal data , table 7: inverter part and section 6.2: packing information . minor text changes. 10-apr-2015 4 minor text edits throughout document updated figure 2: pin layout (bottom view) updated section 6: package information
STGIPS20C60-H 20/20 docid024483 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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